To be able to interconnect the decompressed data obtained in the silx library with the azimuthal integrator provided by pyFAI, without transferring the data back and forth from the device to the processor, the silx team implemented a way to exchange memory objects located on the graphics card between libraries. These results show the validity of the concept which paves the way to interconnecting different algorithms including image analysis and tomography algorithms which are available as part of the silx library. In pyFAI, a couple of advanced statistical analysis tools, recently ported to OpenCL like median filtering in two-dimensional integrated data and sigma-clipped average, could also be good candidates for this kind of direct interconnection.
A prototype unit does not exist at the present time, but the major components have been breadboarded and tested, and a prototype of the case has been constructed. They are currently in the process of final board layout and construction of prototype boards. This process should be complete sometime in April or May. A prototype for IRIS should be available this summer. A major change from the design proposed in 1999 is the incorporation of the originally separate DSS (Disk SubSystem) into a new single-case design, where local storage and networking are with the digitizer function.
A full prototype instrument does not exist at the present time. The unit follows closely the designed proposed in 1999. Most of the boards have been prototyped, with the exception of the main controller. Work on this board is proceeding and should fit with the expected delivery time to IRIS. The main system controller on the Q330 is a DSP unit, rather than some sort of standard microprocessor. Controller power consumption is undetermined at this time, but should fall somewhere in the 100-500 mW range. Analog channels consume about 100 mW per channel. Because unused channels can be powered down, it is expected that the 'standard' instrument will feature 6 channels.
Control set-up and data formats are different from previous Quanterra units. The data come in 1 second packets in compressed format. All data time tags do not include the fir filter lag. Even though data come out every second, data from different sample rates will have different delays due to the fir filters.
DAS development. We are getting close to having initial prototypes for testing. InMarch Quanterra reported on successful testing of the Q330 analogcircuitry and digital processor. All the boards had been built andtested in varying degrees by the end of march. We fully expect to befield testing the Q330 production prototypes this summer.
We will visit RefTek late in May to assess progress on our other new DAS. By the time of the Workshop in June, we should have a reasonably firm date for delivery of initial prototypes for field testing later in the summer. 2b1af7f3a8